The electronics industry is nearing the limits of traditional CMOS (Complementary Metal Oxide) scaling. As traditional Moore's law scaling becomes more difficult, assembly and packaging innovations have enabled continued advances in the electronics industry, by e.g. enabling functional diversification of CMOS integrated circuits and by allowing scaling in the third dimension.
In order to maintain the desired progress in electronics manufacturing, continued increases in functional density and cost per function can be achieved through innovative assembly and packaging-methods.
Wafer level packaging (WLP) is among the innovative approaches to reduce cost and achieve other advantages similar to those obtained from the scaling of front end processes.
Bond or contact pads are formed and exposed on the surfaces of integrated circuit chips where electrical connections are made through the contact pads to connect the chip to a package substrate or to another chip, using wire bonding or flip-chip bonding technologies. Flip chip technologies uses bumps such as C4 (controlled collapse chip connection) or copper pillar bump as the interconnect, and these bumps are formed at the wafer level.
Typically, the formation of bumps requires the use of UBM (under bump metal). That is, the bumps are formed by the electroplating of a seed layer which was previously sputtered on the e.g. substrate. However, during the stripping of the seed layer to leave only the UBM, portions which the bump is formed thereon may be undercut, resulting in potential reliability issues.
In addition, the size of the UBM is typically required to be bigger than the via or opening below it, in order for mechanical alignment mismatches to be better tolerated. Hence, the shrinking of the bump size is restricted by presence of the UBM. This will limit the potential for finer pitches.
Further, the adhesion of UBM to underlying dielectric layers is typically weak and can result in further reliability issues.
The formation of the UBM also requires additional process steps and would require additional equipment such as photo masks. This would incur additional costs, to the wafer fabrication process and also increases process time and reduces throughput.
Thus, there exists a need for an integrated circuit structure, and a method of forming an integrated circuit structure that address or at least ameliorate one or more of the problems described above.